PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Register 007H: Revision/Chip ID/Global Monitoring Update
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R
RESET
TIP
0
X
0
0
0
0
0
0
R
TYPE
ID[4]
ID[3]
ID[2]
ID[1]
ID[0]
R
R
R
R
R
RESET:
The RESET bit allows software to asynchronously reset the QDSX. The
software reset is equivalent to setting the RSTB input pin low. When a logic 1
is written to RESET, the QDSX is reset. When a logic 0 is written to RESET,
the reset is removed. The RESET bit must be explicitly set and cleared by
writing the corresponding logic value to this register.
TIP:
The TIP bit is set to a logic one when any value with Bit 7 set to logic 0 is
written to this register. Such a write initiates an accumulation interval transfer
and loads all the performance meter registers in the LCV_PMON and PRSM
blocks. TIP remains high while the transfer is in progress, and is set to a logic
zero when the transfer is complete. TIP can be polled by a microprocessor to
determine when the accumulation interval transfer is complete.
TYPE:
The chip identification TYPE bit is set at a logic 0.
ID[4:0]:
The ID[4:0] bits allows software to identify the version level of the device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
67
PMC [ PMC-SIERRA, INC ]
