PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Register 006H or 106H: MasterTest
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
W
Reserved
A_TM[7]
A_TM[6]
PMCTST
DBCTRL
IOTST
0
X
X
X
X
0
W
R/W
W
HIZDATA
HIZIO
X
0
R/W
This register is used to enable QDSX test features. All bits, except PMCTST and
A_TM[7:6] are reset to zero by a hardware reset of the QDSX.
Register 006H and 106H access the same register. The "mirroring" of this
register to the two register spaces is done to ensure access to this register is
available if the A[8] address pin is tied to logic 1 or 0.
Reserved:
This bit must be set to logic 0 for proper normal mode operation.
Eng: HWTST:
A_TM[6]:
The state of the A_TM[6] bit internally replaces the input address line A[6]
when PMCTST is set. This allows for more efficient use of the PMC
manufacturing test vectors.
PMCTST:
The PMCTST bit is used to configure the QDSX for PMC's manufacturing
tests. When PMCTST is set to logic one, the QDSX microprocessor port
becomes the test access port used to run the PMC manufacturing test
vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and can be
cleared by setting CSB to logic one or by writing logic zero to the bit.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
65
PMC [ PMC-SIERRA, INC ]
