PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Figure 9
- E1 jitter tolerance with ALGSEL = 0
Me a sure m e nt Lim it
Me a sure d
10
CDRC Jitte r
To le ra nc e
(ALG SEL = 0)
1.0
G823 Jitte r
To le ra nc e
Sp e c ific a tio n
0.1
0.01
.
Jitte r Fre q ue nc e (Hz)
9.3
Line Code Violation Performance Monitor (LCV_PMON)
The Line Code Violation Performance Monitor function is provided by the
(LCV_PMON) block. This block accumulates line code violation events with
saturating counters over consecutive intervals as defined by the period of the
supplied transfer clock signal. When the transfer clock signal is applied, the
LCV_PMON block transfers the counter values into holding registers and resets
the counters to begin accumulating events for the interval.The counters are reset
in such a manner that error events occurring during the reset are not missed. If
enabled, an interrupt is generated whenever counter data is transferred into the
holding registers. If the holding registers are not read between successive
transfer clocks, the OVR register bit in the LCV_PMON Interrupt Enable/Status
register (014H, 054H, 094H, and 0D4H) is asserted.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
38
PMC [ PMC-SIERRA, INC ]
