PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
pulses from RSLC are passed directly to the SDP[X] and SDN[X] outputs
respectively.
The input jitter tolerance for DSX-1 interfaces complies with the Bellcore
document TA-TSY-000170 and with the AT&T specification TR 62411.The
tolerance is measured with a QRSS sequence (220-1 with 14 zero restriction).
The CDRC block provides two algorithms for clock recovery that result in differing
jitter tolerance characteristics.The first algorithm (when the ALGSEL register bit
in the CDRC Configuration register (010H, 050H, 090H, 0D0H) is logic 0)
provides good low frequency jitter tolerance, but the high frequency tolerance is
close to the TR 62411 limit.The second algorithm (when ALGSEL is logic 1)
provides much better high frequency jitter tolerance, approaching 0.5UIpp (Unit
Intervals peak-to-peak), at the expense of the low frequency tolerance; the low
frequency tolerance of the second algorithm is approximately 80% of that of the
first algorithm. The DSX-1 jitter tolerance with ALGSEL set to 1 and to 0 is
shown in Figure 7.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
35
PMC [ PMC-SIERRA, INC ]
