PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Generation of the individual LCV_PMON transfer clocks for specific quadrants of
the QDSX is performed by writing to any of the LCV_PMON counter register
locations of the particular quadrant. A global performance monitor transfer clock
signal is generated by writing to register 007H. This will latch the counter values
in all the LCV_PMONs and PRSMs of the QDSX. The holding register
addresses are contiguous to facilitate polling operations.
9.4
Inband Loopback Code Detector (IBCD)
The Inband Loopback Code Detection function is provided by the IBCD block.
This block detects the presence of either of two programmable loopback code
sequences, ACTIVATE and DEACTIVATE, in framed or unframed DS-1 data
streams.The inband code sequences are expected to be overwritten by the
framing bit in framed data streams. Each code sequence is defined as the
repetition of the programmed code in the PCM stream for at least 5.1 seconds.
The code sequence detection and timing is compatible with the specifications
defined in T1.403, TA-TSY-000312, and TR-TSY-000303. ACTIVATE and
DEACTIVATE code indication is provided through internal register bits. An
interrupt is generated to indicate when either code status has changed. The
IBCD can detect inband loopback codes in the recovered unipolar receive data
when configured to be in the receive data stream or in the unipolar input transmit
data when configured to be in the transmit data stream. When enabled in the
receive stream, the IBCD can be configured to enable and disable line loopback
on detection of inband loopback activate and deactivate sequences.
9.5
Pseudo-Random Bit Sequence Monitor (PRSM)
The Pseudo-Random Sequence Monitor (PRSM) block monitors the recovered
15
PCM data for the presence of an unframed 2 -1 test sequence as defined in
Recommendation O.151 and accumulates bit errors detected using this pseudo-
random pattern.The test sequence may optionally be inverted before being
checked against the generated pattern. The sequence monitor does not
synchronize to an all zeroes pattern. The PRSM declares synchronization when
less than 15 sequence errors are detected in 256 bit periods. Using this
threshold, synchronization is achieved within 663 µsec (for DSX-1 applications)
-2
or 500 µsec (for E1 applications), 99.7% of the time, in the presence of a 10 bit
error rate. Once synchronized, the mean time between loss of synchronization
events is greater than 136 minutes (for DSX-1) or 103 minutes (for E1), in the
-2
presence of a 10 bit error rate. When the test sequence is no longer present
(as indicated by a bit error rate of 0.5) the PRSM will lose synchronization in 48
µsec (for DSX-1) or 36 µsec (for E1), more than 99% of the time. In the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
39
PMC [ PMC-SIERRA, INC ]
