PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
this data in a FIFO. The data emerges from the DJAT timed to the jitter
attenuated clock and is transferred to the XPLS block for transmission.
The DJAT generates a "jitter-free" 1.544/2.048 MHz clock by adaptively dividing
the 24x XCLK input according to the phase difference between the generated
"jitter-free" clock and the input data clock to DJAT (TCLKI[X] when DJAT is in the
default transmit path, or the recovered clock RCLKO[X] if in line loopback mode
or when DJAT is configured to be on the receive path). Phase variations in the
input clock with a jitter frequency above 8.8 Hz (for the E1 format) or 6.6 Hz (for
the T1 formats) are attenuated by 6 dB per octave of jitter frequency. Phase
variations below these jitter frequencies are tracked by the "jitter-free" clock.
Jitter Characteristics
The DJAT provides excellent jitter tolerance and jitter attenuation while
generating minimal residual jitter. It can accommodate up to 28 UIpp of input
jitter at jitter frequencies above 6 Hz for DSX-1 interfaces or 9 Hz for E1
interfaces. For jitter frequencies below 6/9 Hz, more correctly called wander, the
tolerance increases 20 dB per decade. In most applications DJAT will limit jitter
tolerance at lower jitter frequencies only. The DJAT block meets the low
frequency jitter tolerance requirements of AT&T TR 62411 for DSX-1 interfaces,
and ITU-T G.823 for E1 interfaces.
Outgoing jitter may be dominated by the generated residual jitter in cases where
the incoming jitter is insignificant. This residual jitter is directly related to the use
of the 24x clock for the digital phase locked loop.
For DSX-1 interfaces, DJAT meets the jitter attenuation requirements of AT&T TR
62411. DJAT meets the implied jitter attenuation requirements for a TE or an
NT1 specified in ANSI T1.408, and for a type II customer interface specified in
ANSI T1.403.
For E1 interfaces, DJAT meets the jitter attenuation requirements of ITU-T
Recommendations G.737, G.738, G.739, and G.742.
JitterTolerance
Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a
device can accept without exceeding its linear operating range, or corrupting
data. For DJAT, the input jitter tolerance is 29 Unit Intervals peak-to-peak (UIpp)
for a DSX-1 interface with a worst case frequency offset of 354 Hz. The input
jitter tolerance is 35 UIpp for an E1 interface with a worst case frequency offset
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
42
PMC [ PMC-SIERRA, INC ]
