PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Table 2
-
Turns
Ratio
OCL (mH
min.)
Cw/w (pF
max.)
LL (µH
max.)
DCR pri.
(Ω max.)
DCR sec.
(Ω max.)
(PRI:SEC)
1:2
1.20
35
0.80
0.80
1.2
where
OCL is the open-circuit inductance,
Cw/w is the inter-winding capacitance,
LL
is the leakage inductance, and
DCR is the DC resistance.
PMC-Sierra has verified the operation of the RSLC functional block with the
following transformers:
• Pulse Engineering PE64931 (1:1:1) and PE64952 (1:2CT)
• BH Electronics 500-1775 (1:1:1) and 500-1777 (1:2CT)
Many manufacturers produce dual transformers containing the 1:2 CT and 1:1.36
transformers necessary for the receiver and transmitter circuits. PMC-Sierra has
verified the operation of XPLS and RSLC with the following dual parts:
• Pulse Engineering PE64952
• Pulse Engineering PE65774 (for extended temperature range)
• BH Electronics500-1777
9.2
Clock and Data Recovery (CDRC)
The Clock and Data Recovery function is contained in the CDRC block and is
active when clock recovery is not disabled. The CDRC provides clock and data
recovery, B8ZS/HDB3 decoding, bipolar violation detection, and loss of signal
detection. It recovers the clock from the incoming RZ data pulses using a digital
phase-locked-loop and recovers the NRZ data. Loss of signal is declared after
exceeding a programmed threshold of 10, 31, 63, or 175 consecutive bit periods
of the absence of pulses on both the positive and negative line pulse inputs and
is removed after the occurrence of a single line pulse. If enabled, a
microprocessor interrupt is generated when a loss of signal is detected and when
the signal returns. When the CDRC is disabled, the positive and negative sliced
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
34
PMC [ PMC-SIERRA, INC ]
