PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
presence of random data (a bit error rate of 0.5) the mean time between false
synchronization events is greater than 184 years.
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The PRSM can be configured to detect either an inverted or a noninverted 2 -1
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pseudorandom bit sequence (PRBS). An inverted 2 -1 PRBS will contain at
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most 15 consecutive zeroes, while a non-inverted 2 -1 PRBS will contain at
most 14 consecutive zeroes.
The PRSM block accumulates bit error events with a saturating counter over
consecutive intervals as defined by the period of a latch clock signal. An internal
latch clock signal, unique to each PRSM in the QDSX, can be generated by
writing to any of the particular PRSM holding registers. A write to any PRSM
holding register in quadrant 1 of the QDSX generates an internal latch clock
pulse for the PRSM in quadrant 1. Similarly a write to any PRSM holding register
in any other quadrant generates an internal latch clock pulse for the PRSM in
that same quadrant. A write to register 007H will generate a global performance
monitor latch clock signal. A write to this register will toggle the internal latch
clock pulses to all four PRSMs as well as all four LCV_PMONs (which operate in
a similar fashion).
If enabled, an interrupt is generated whenever counter data is transferred into the
PRSM holding registers. If the holding registers are not read between
successive transfer clocks, the overrun (OVR) bit in the PRSM Control/Status
Register is set.
An indication of whether or not the pseudorandom sequence monitor is
synchronized is provided via the PRSM Control/Status register and, if enabled,
an interrupt is generated whenever a loss of synchronization or
resynchronization occurs. The PRSM can detect pseudorandom sequences in
the receive stream, or in the transmit stream if TDUAL is set to logic 0. PRSM
functions are available only when microprocessor access is available (MICROEN
is high).
9.6
Timing Options (TOPS)
If jitter attenuation is required, then XCLK must be a 24X clock, and TOPS will
generate the 8X clock either from the DJAT PLL smoothed 8X clock from
quadrant 1, or by dividing XCLK by 3. This 8X clock will be presented on
CLKO8X. Otherwise, XCLK is expected to be an 8X high speed clock and
TOPS will simply buffer it before passing it off as the internal high speed
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
