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HDMP-1638G 参数 Datasheet PDF下载

HDMP-1638G图片预览
型号: HDMP-1638G
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, 1-Trnsvr, Bipolar, PQFP64,]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 18 页 / 266 K
品牌: PMC [ PMC-SIERRA, INC ]
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V
*
CC  
Transceiver Power Supply Bypass  
and Loop Filter Capacitors  
V
CC  
If desired, bypass capacitors may  
be used on the power supply pins  
of the HDMP-1638G. All bypass  
chip capacitors are 0.1 μF. The  
C
PLLR  
V
_RXA and V _TXA pins are  
CC  
CC  
RXCAP0  
GND_TXHS  
the analog power supply pins for  
the PLL sections. The supply into  
these pins should be clean with  
minimum noise. Use of capacitors  
as shown in Figure 12 is  
mandatory for these pins. The PLL  
loop filter capacitors and their pin  
locations are also shown on Figure  
12. Notice that only two capacitors  
GND_RXTTL  
V
V
_RXTTL  
_RXTTL  
V
CC  
CC  
HDMP-1638G  
TOP VIEW  
CC  
are required; C  
for the trans-  
PLLT  
mitter and C  
for the receiver.  
PLLR  
GND_TXTTL  
GND_TXA  
Nominal capacitance is 0.1 μF. The  
maximum voltage across the  
capacitors is on the order of 1 volt,  
so the capacitor can be a low  
voltage type and physically small.  
The PLL capacitors are to be  
placed physically close to the  
appropriate pins on the HDMP-  
1638G. Keeping the lines short will  
prevent them from picking up any  
stray noise from surrounding lines  
or components.  
TXCAP1  
GND_RXTTL  
C
V
PLL  
CC  
V
*
CC  
* SUPPLY VOLTAGE INTO V _RXA AND V _TXA SHOULD BE FROM A LOW NOISE  
CC CC  
SOURCE. ALL BYPASS CAPACITORS AND PLL FILTER CAPACITORS ARE 0.1 µF.  
Figure 12. Power supply bypass.  
Start Up Procedure:  
The transceiver startup procedure(s) and the following conditions:  
V
= +3.3 V 5% and REFCLK = 125 MHz 100 ppm.  
CC  
After the above conditions have been met, apply valid data using a  
balanced code such as 8B/Figure 13: Mechanical Dimensions of  
HDMP-1638G.  
15  
PMC-Sierra, Inc. - Not Recommended for New Designs  
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