TRx I/ O Definition
Name
Pin Type
Signal
BYTSYNC
47
O-TTL
HS_IN
HS_IN
I-TTL
Byte Sync Output: An active high output. Used to indicate detection of either a comma
character (0011111XXX). It is only active when ENBYTSYNC is enabled.
-DINA
+DINA
52
53
Serial Data Inputs: High speed inputs. Serial data is accepted from the DINA inputs
when LOOPEN and RXSEL are both low.
-DINB
+DINB
55
56
Serial Data Inputs: High speed inputs. Serial data is accepted from the DINB inputs
when LOOPEN is low and RXSEL high.
RXSEL
13
Serial Input Select: If this pin is held low then DINA inputs are parallelized. If this pin is
held high then DINB inputs are parallelized.
-DOUTA
+DOUTA
59
60
HS_OUT Serial Data Outputs: High speed outputs. These lines are active when LOOPEN is set
low. When LOOPEN is set high, these outputs are held static at logic 1. If unused,
remove the 150 Ω pulldown resistors to save power.
-DOUTB
+DOUTB
62
63
HS_OUT Serial Data Outputs: High speed outputs. These lines are active when LOOPEN is set
low. When LOOPEN is set high, these outputs are held static at logic 1. If unused,
remove the 150 Ω pulldown resistors to save power.
ENBYTSYNC 24
I-TTL
Enable Byte Sync Input: When high, turns on the internal byte sync function to allow
clock synchronization to a comma character (0011111XXX). When the line is low, the
function is disabled and will not reset registers and clocks, or strobe the BYTSYNC line.
GND
21
25
S
S
Logic Ground: Normally 0 volts. This ground is used for internal PECL logic. It should be
isolated from the noisy TTL ground as well as possible.
GND_RXA
51
Analog Ground: Normally 0 volts. Used to provide a clean ground plane for the receiver
PLL and high-speed analog cells.
GND_RXHS 57
S
S
Ground: Normally 0 volts.
GND_RXTTL 32
TTL Receiver Ground: Normally 0 volts. Used for the TTL output cells of the receiver
33
46
section.
GND_TXA
15
S
Analog Ground: Normally 0 volts. Used to provide a clean ground plane for the PLL and
high-speed analog cells.
GND_TXHS
1
S
S
Ground: Normally 0 volts.
GND_TXTTL 14
TTL Transmitter Ground: Normally 0 volts. Used for the TTL input cells of the transmitter
section.
N/C
27,12
These pins are connected to an isolated pad and have no functionality. They may be left
open, however, TTL levels may also be applied to these pins.
LOOPEN
19
I-TTL
O-TTL
PECL
Loopback Enable Input: When set high, the high speed serial signal is internally
wrapped from the transmitter’s serial loopback outputs back to the receiver’s loopback
inputs. Also when in loopback mode, the DOUT outputs are held static at logic 1. When
set low, DOUT outputs and DIN inputs are active.
RBC1
RBC0
30
31
Receiver Byte Clocks: The receiver section recovers two 62.5 MHz receive byte
clocks. These two clocks are 180 degrees out of phase. The receiver parallel data out
puts are alternately clocked on the rising edge of these clocks. The rising edge of RBC1
aligns with the output of the comma character (for byte alignment) when detected.
+REFCLK
-REFCLK
22
23
Reference Clock and Transmit Byte Clock: A 125 MHz clock supplied by the host
system. The transmitter section accepts this signal as the frequency reference clock. It
is multiplied by 10 to generate the serial bit clock and other internal clocks. The transmit
side also uses this clock as the transmit byte clock for the incoming parallel data
TX[0]..TX[9]. It also serves as the reference clock for the receive portion of the
transceiver.
13
PMC-Sierra, Inc. - Not Recommended for New Designs
PMC [ PMC-SIERRA, INC ]
