TransDimension Inc.
Interfacing TD242LP to Intel StrongArm SA1110 Processor
When R2 is installed and port 1 operates as a host, a sufficiently large capacitor (more than 120
µF) is applied to the VBus of port 1 per USB specification. When R1 is installed and port 1
operates as an OTG port, a capacitor between 1uF and 6.5uF is applied per USB specification.
Ferrite beads are inserted in the VBus and ground circuits for EMI reduction.
Software Considerations
Operating as a USB OTG controller, the TD242LP implements the HNP/SRP (Host Negotiation
protocol and Session request Protocol), which configures Port 1 circuit dynamically. For details,
please contact TransDimension technical support for details.
4. Power and Ground
I/O Voltage
Tie the VDDW pins to 3.3V so the I/O pins operate at 3.3V. All logic pins are LVCTTL
compatible, and 5V tolerant.
Core Voltage
Tie the VDD2.5 and VDD2.5A pins to the VREGOUT pin to use the internal voltage regulator of
the TD242LP to drive its core voltage. A minimum 3.3uF capacitor is required on this circuit.
The ENVREG pin must be tied to 3.3V to enable the internal voltage regulator (see Section 2.2).
VDD2.5 and VDD2.5A should be tied directly together.
3.3V Supply
Tie the VDD3.3 and VDD3.3A pins directly to 3.3V.
Ground
Tie the VSS (digital GND) and VSSA (analog GND) directly to the ground plane.
5. Reference Design Schematics
The schematic drawing below is based on several assumptions made in the above discussion. It
must be modified according to one’s application. There are two pages of the schematics that
show the connections for the BGA64 and the LQFP64 packages. Choose the appropriate page per
the system requirements.
TransDimension, Inc.
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