Functional Overview
PLX Technology, Inc.
4.2
PCI-Compatible Software Model
The PEX 8532 can be thought of as a hierarchy of PCI-to-PCI bridges, with one upstream PCI-to-PCI
bridge and one or more downstream PCI-to-PCI bridges connected by a virtual internal bus. (Refer to
Figure 4-4.) PCI-to-PCI bridges are compliant with the PCI and PCI Express system models. Figure 4-4
illustrates the concept of hierarchical PCI-to-PCI bridges, with the bus in the middle being the virtual
PCI Bus. The Configuration Space registers (CSRs) in the upstream PCI-to-PCI bridge are accessible by
Type 0 Configuration requests targeting the upstream bus interface. The upstream port captures the
Type 0 Configuration Write Target Bus Number and Device Number. The upstream port uses this
Captured Bus Number and Captured Device Number as part of the Requester ID and Completer ID for
the requests and completions generated by the upstream port.
The CSRs in the downstream port PCI-to-PCI bridges are accessible by Type 1 Configuration requests
received at the upstream port that target the virtual internal bus, by having a Bus Number value that
matches the upstream bridge’s Secondary Bus Number value. Each downstream bridge is associated
with a unique Device Number, as explained in Section 4.1.2.
The CSRs of downstream devices are hit in two ways. If the Configuration request matches the
PEX 8532 downstream port Secondary Bus Number, the PEX 8532 converts the Type 1 Configuration
request into a Type 0 Configuration request. However, if the Bus Number does not match the Secondary
Bus Number, but falls within the Subordinate Bus Number range, the Type 1 Configuration request is
forwarded out of the PEX 8532, unchanged.
After all PCI devices have been located and assigned Bus and Device Numbers, software can assign
a Memory map and I/O map. Requests (Memory or I/O) go downstream if they fall within a bridge’s
Base and Limit range. In the PEX 8532, each downstream bridge has its own Base and Limit. The
Request (Memory or I/O) goes upstream if it does not target anything within the upstream bridge’s Base
and Limit range.
Completions route by the Bus Number established in the Configuration registers. If the Bus Number
is in the Secondary or Subordinate range, the packet goes downstream; otherwise, the packet
goes upstream.
Figure 4-4. PEX 8532 System Configuration Propagation
Configuration
Propagation
Upstream
Port
Virtual PCI Bus
Upstream
P-P Bridge
P-P
Downstream
P-P Bridges
P-P
P-P
P-P
P-P
P-P
P-P
P-P
Downstream
Ports
Upstream Station
Downstream Station
56
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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