Functional Overview
PLX Technology, Inc.
4.1.2
Station and Port Functions
Each port implements the PCI Express Base r1.0a Physical, Data Link, and Transaction layers. Each
PCI Express station can support up to 16 integrated Serializer/De-serializer (SerDes) modules.The
SerDes modules provide the 32 PCI Express hardware interface lanes.
The lanes can be combined, for a total of one to four PCI Express ports per station. If the upstream port
is in the other station, all enabled ports in the current station are downstream ports. Lanes from different
stations cannot be combined to form ports.
From the system model viewpoint, each PCI Express port is a virtual PCI-to-PCI bridge device with its
own set of PCI Express Configuration registers. The BIOS enumerates the PEX 8532 ports, using either
Conventional PCI Configuration access or PCI Express Enhanced access.
The PEX 8532 port width is configurable by way of Strapped signal balls, or serial EEPROM after reset.
The final port width can be made narrower by auto-lane width negotiation, as described in the
PCI Express Base r1.0a.
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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