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PEX8532-BB25BI 参数 Datasheet PDF下载

PEX8532-BB25BI图片预览
型号: PEX8532-BB25BI
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PBGA680, 35 X 35 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-680]
分类和应用: 时钟数据传输PC外围集成电路
文件页数/大小: 512 页 / 4374 K
品牌: PLX [ PLX TECHNOLOGY ]
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Signal Ball Description  
PLX Technology, Inc.  
Table 3-4. PEX 8532 Hot Plug Signals – 72 Balls (Cont.)  
Signal Name  
Type  
Location  
Description  
Combination of Hot Plug PRSNT1# and PRSNT2# Input  
for Station 0 Ports (4 Balls)  
Active-Low input connected to the slot’s PRSNT2# signal, which on the add-in  
board connects to the slot’s PRSNT1# signal, which is normally grounded on  
the PRSNT2# signal at the motherboard slot. A change in the HP_PRSNTx#  
Input signal state is latched in the Slot Status register Presence Detect  
Changed bit (offset 80h[19]), and the state change can assert an interrupt  
to notify the Host of board presence or absence.  
When the following conditions exist:  
I
P34, AC34,  
R1, AD1  
HP_PRSNT[3:0]#  
PUa  
HP_PRSNTx# is not masked (Slot Control register Presence Detect  
Changed Enable bit (offset 80h[3]=1), and  
Slot Control register Hot Plug Interrupt Enable bit is set  
(offset 80h[5]=1),  
an interrupt (MSI, or INTx message, both mutually exclusive) can be  
generated.  
Note: HP_PRSNTx# is internally de-bounced, but must remain stable for  
at least 10 ms.  
Combination of Hot Plug PRSNT1# and PRSNT2# Input  
for Station 1 Ports (4 Balls)  
Refer to description for HP_PRSNT[3:0]#.  
I
AA33, M33,  
AB2, N2  
HP_PRSNT[11:8]#  
PUa  
Active-Low Hot Plug Power Enable Output for Station 0 Ports (4 Balls)  
Active-Low Slot Control Logic output that controls the slot power state.  
When this signal is Low, power is enabled to the slot.  
Enabled when the Slot Capabilities register Power Controller Present bit  
is set (offset 7Ch[1]=1).  
When software turns the slot’s Power Controller On or Off (Slot Control  
register Power Controller Control bit, offset 80h[10]), a Command  
Completed interrupt can be generated to notify the Host that the command  
has been executed.  
When the following conditions exist:  
N34, AB34,  
P1, AC1  
HP_PWREN[3:0]#  
O
Slot Control register Command Completed Interrupt Enable bit  
is not masked (offset 80h[4]=1), and  
Slot Control register Hot Plug Interrupt Enable bit is set  
(offset 80h[5]=1),  
an interrupt (MSI, or INTx message, both mutually exclusive) can be generated  
to the Host.  
When HP_MRLx# is enabled [Slot Capabilities register MRL Sensor Present  
bit is set (offset 7Ch[2]=1)], HP_MRLx# input assertion enables Hot Plug  
output sequencing to turn On the slot’s power, by asserting HP_PWRENx#  
after reset or under software control.  
Active-Low Hot Plug Power Enable Output for Station 1 Ports (4 Balls)  
Refer to description for HP_PWREN[3:0]#.  
AB33, N33,  
AC2, P2  
HP_PWREN[11:8]#  
O
22  
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book  
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6  
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