February, 2007
Hot Plug Signals
Table 3-4. PEX 8532 Hot Plug Signals – 72 Balls (Cont.)
Signal Name
Type
Location
Description
Reference Clock Enable Output for Station 0 Ports (4 Balls)
Active-Low output that, when enabled, allows external REFCLK
to be provided to the slot.
Enabled when the Slot Capabilities register Power Controller Present bit
is set (offset 7Ch[1]=1), and controlled by the Slot Control register
Power Controller Control bit (offset 80h[10]).
U34, AF34,
V1, AG1
HP_CLKEN[3:0]#
O
The time delay from HP_PWRENx# output assertion to HP_CLKENx#
output assertion is programmable (through serial EEPROM load) from 16 ms
(default) to 128 ms, in the HPC Tpepv Delay field (offset 1E0h[4:3]).
Reference Clock Enable Output for Station 1 Ports (4 Balls)
Refer to description for HP_CLKEN[3:0]#.
V33, J33,
W2, K2
HP_CLKEN[11:8]#
O
Hot Plug Manually Operated Retention Latch Sensor Input
for Station 0 Ports (4 Balls)
Active-Low input that triggers Slot Control Logic. Directly connected
to an optional MRL Sensor that is logic High when the latch is not closed.
HP_MRLx# input assertion enables Hot Plug output sequencing to turn
On the slot’s power (HP_PWRENx# and HP_PWRLEDx#) and clock
(HP_CLKENx#), and de-assert Reset (HP_PERSTx#) after reset or under
software control.
A change in the HP_MRLx# Input signal state is latched in the Slot Status
register MRL Sensor Changed bit (offset 80h[18]), and the state change can
assert an interrupt to notify the Host of a change in the MRL Sensor state.
When the following conditions exist:
•
HP_MRLx# is not masked (Slot Control register MRL Sensor Changed
Enable bit, offset 80h[2]=1), and
I
L34, Y34,
M1, AA1
HP_MRL[3:0]#
PUa
•
Slot Control register Hot Plug Interrupt Enable bit is set
(offset 80h[5]=1),
an interrupt (MSI, or INTx message, both mutually exclusive) can be
generated.
If the associated Hot Plug-capable downstream port connects to a PCI Express
board slot that does not implement an MRL Sensor, HP_MRLx# is normally
connected to HP_PRSNTx# and a pull-up resistor, with the common node
connected to the PRSNT2# signal(s) at the slot. If the associated Hot Plug-
capable downstream port instead connects directly to a device (in which case
Hot Plug is not used), pull HP_MRLx# Low.
Note: HP_MRLx# is internally de-bounced, but must remain stable
for at least 10 ms. HP_MRLx#, if enabled, is not de-bounced when sampled
immediately after reset.
Hot Plug Manually Operated Retention Latch Sensor Input
for Station 1 Ports (4 Balls)
Refer to description for HP_MRL[3:0]#.
I
AD33, R33,
AE2, T2
HP_MRL[11:8]#
PUa
Active-Low Reset Output for Station 0 Ports (4 Balls)
Active-Low Hot Plug output used to reset the slot. Controlled by the
Slot Control register Power Controller Control bit (offset 80h[10]).
R34, AD34,
T1, AE1
HP_PERST[3:0]#
HP_PERST[11:8]#
O
O
Active-Low Reset Output for Station 1 Ports (4 Balls)
Refer to description for HP_PERST[3:0]#.
Y33, L33,
AA2, M2
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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