February, 2007
PCI Express Capability Registers
Register 11-27. 78h Link Status and Control (All Ports) (Cont.)
Serial
EEPROM
Bit(s)
Description
Ports
Type
Default
Link Status
Link Speed
19:16
RO
Yes
1h
Set to 1h, as required by the PCI Express Base r1.0a
for a 2.5 Gbps PCI Express link.
Negotiated Link Width
Link width is determined by negotiated value with attached port/lane:
00_0001b = x1
00_0010b = x2
00_0100b = x4
00_1000b = x8
01_0000b = x16
25:20
RO
Yes
00_0001b
All other values are not supported. The value in this field is undefined when
the link is not up.
Training Error
Upstream
RO
RO
RO
No
Yes
No
0
0
0
Not valid for the upstream port.
26
When set to 1, indicates that the corresponding PEX 8532 port
detected a Link Training error.
Downstream
Upstream
Link Training
Not valid for the upstream port.
27
28
When set to 1, indicates that the corresponding PEX 8532
downstream port requested link training and either the link
training is in process or about to start.
Downstream
RO
No
0
Slot Clock Configuration
0 = Indicates PEX 8532 uses an independent clock
1 = Indicates PEX 8532 uses the same physical reference clock that the platform
provides on the connector
HwInit
Yes
0
31:29 Reserved
000b
a. The port receiver must be capable of entering L0s state, regardless of whether the state is disabled.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
181
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