February, 2007
PCI Express Capability Registers
Register 11-26. 74h Link Capabilities (All Ports)
Serial
EEPROM
Bit(s)
Description
Type
Default
Maximum Link Speed
3:0
RO
Yes
0001b
Set to 0001b, as required by the PCI Express Base r1.0a.
Maximum Link Width
9:4
RO
RO
No
Strap levels
Actual link width is set by signal ball strapping options. The PEX 8532 Maximum
Link Width is x16 = 01_0000b.
Active State Power Management (ASPM) Support
Indicates the level of ASPM supported by the port.
01b = L0s link power state entry is supported
10b = L0s and L1 link power states are supported
All other values are reserved.
11:10
Yes
11b
L0s Exit Latency
14:12
17:15
RO
RO
No
101b
101b = Corresponding PEX 8532 port L0s Exit Latency is between 1 and 2 µs
L1 Exit Latency
Yes
101b
0-0h
101b = Corresponding PEX 8532 port L1 Exit Latency is between 16 and 32 µs
23:18 Reserved
Port Number
The Port Number is set by signal ball strapping options:
STRAP_STN0_PORTCFG[4:0] – Ports 0, 1, 2, 3
STRAP_STN1_PORTCFG[4:0] – Ports 8, 9, 10, 11
Set by strap
levels
31:24
HwInit
No
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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