February, 2007
PCI Express Capability Registers
Register 11-29. 80h Slot Status and Control (All Ports) (Cont.)
Serial
EEPROM
Bit(s)
Description
Ports
Type
Default
MRL Sensor Changed Enable
Upstream
RO
RW
RO
No
0
Not valid for the upstream port.
0 = Function is disabled
1 = Enables software notification with a Hot Plug
interrupt if the port is in the D0 Power State
(Power Management Status and Control register
Power State field, offset 44h[1:0]=00b), or with
a PME message if the port is in the D3hot state
(offset 44h[1:0]=11b), for an MRL Sensor
Changed event on the corresponding PEX 8532
downstream port.
2
Downstream
Upstream
Yes
No
0
0
Presence Detect Changed Enable
Not valid for the upstream port.
0 = Function is disabled
1 = Enables software notification with a Hot Plug
interrupt if the port is in the D0 Power State
(Power Management Status and Control register
Power State field, offset 44h[1:0]=00b), or with
a PME message if the port is in the D3hot state
(offset 44h[1:0]=11b), for a Presence Detect
Changed event on the corresponding PEX 8532
downstream port.
3
A Presence Detect Changed event is triggered from
one of two sources, depending on the state of the
HPC Inband Presence Detect Enable bit (1E0h[5]):
Downstream
RW
Yes
0
•
If the HPC Inband Presence Detect Enable bit
is cleared (offset 1E0h[5]=0, default), Presence
Detect is input from the HP_PRSNTx# signal
on the corresponding PEX 8532 downstream
port
•
If the HPC Inband Presence Detect Enable bit
is set (offset 1E0h[5]=1), Presence Detect is
input from the SerDes Receiver Detect on the
corresponding PEX 8532 downstream port
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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