PEX 8532 Transparent Mode Port Registers
PLX Technology, Inc.
Register 11-27. 78h Link Status and Control (All Ports)
Serial
Default
Bit(s)
Description
Ports
Type
EEPROM
Link Control
Active State Power Management (ASPM) Control
00b = Disables L0s and L1 Entries for the corresponding PEX 8532 porta
01b = Enables only L0s Entry
1:0
RW
Yes
00b
10b = Enables only L1 Entry
11b = Enables both L0s and L1 Entries
2
3
Reserved
0
0
Read Completion Boundary (RCB)
RO
Yes
Cleared to 0, as required by the PCI Express Base r1.0a.
Link Disable
Upstream
RO
RW
RO
No
Yes
No
0
0
0
Not valid for the upstream port.
4
5
Setting to 1 places the link on the corresponding PEX 8532
downstream port to the Disabled Link Training state.
Downstream
Upstream
Retrain Link
Not valid for the upstream port.
For PEX 8532 ports, when read, always returns 0.
Downstream
RW
Yes
0
Writing 1 to this bit causes the corresponding PEX 8532
downstream port to initiate retraining of its PCI Express link.
Common Clock Configuration
0 = Corresponding PEX 8532 port and the device at the other end of the
corresponding port’s PCI Express link are operating with an asynchronous
reference clock
6
RW
Yes
0
1 = Corresponding PEX 8532 port and the device at the other end of the
corresponding port’s PCI Express link are operating with a distributed common
reference clock
Extended Sync
Set to 1 causes the corresponding PEX 8532 port to transmit:
7
RW
Yes
0
•
•
•
4,096 FTS Ordered-Sets in the L0s state,
Followed by a single SKIP Ordered-Set prior to entering the L0 state,
Finally, transmission of 1,024 TS1 Ordered-Sets in the Recovery state.
15:8
Reserved
00h
180
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
