Software Architecture
PLX Technology, Inc.
7.2
Configuration Mechanisms
The PEX 8532 supports the two Configuration mechanisms described in the PCI Express Base r1.0a:
• PCI r2.3-Compatible Configuration Mechanism
This mechanism supports 100ꢀ binary compatibility with the PCI r2.3 and its corresponding
Bus Enumeration and Configuration software. The mechanism allows access to the lower
256 bytes (64 DWords) of the 4-KB Configuration space of each port. Access to the entire
4-KB Configuration Space requires 10 Address bits, which are defined in a PCI Express
Configuration Request packet to include a 6-bit Register Number field and a 4-bit Extended
Register Number field. The mechanism maps all six of its Address bits into the Register Number
field, and clears the Extended Register Number field in the packet to 0h. Therefore, the mechanism
cannot access the upper 960 DWords (PCI Express Extended Configuration space) that are
implemented in each port.
• PCI Express Enhanced Configuration Mechanism
This mechanism increases the size of available Configuration space and optimizes Configuration
mechanisms. The mechanism allows access to the entire 4-KB Configuration space defined
by the PCI Express Base r1.0a. Registers within the PEX 8532 that are defined by the
PCI Express Base r1.0a can be accessed by this mechanism. PEX 8532 device-specific registers
(which are not defined by the PCI Express Base r1.0a) cannot be accessed by this mechanism.
The PEX 8532 also supports a third Configuration mechanism:
• PLX-Specific Memory-Mapped Configuration Mechanism
This mechanism supports access to all PEX 8532 registers, with the use of Memory Read and
Memory Write commands and a 128-KB Address space that includes the 4-KB register sets
of all ports, that is located at the Base address assigned to the upstream port’s Base Address 0
and Base Address 1 registers (BAR0 and BAR1, offsets 10h and 14h, respectively).
From a software point of view, each PEX 8532 port is a PCI-to-PCI bridge. A PCI-to-PCI bridge must
have uniquely assigned Bus and Device Numbers. The upstream port has its own Primary Bus Number,
while all downstream ports share the same (internal) Bus Number and different Device Numbers.
For further details, refer to Section 11.4, “Register Access.”
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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