Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
MODE
FEATURE
SCHEMATIC
12
Data path:
• Input ADC to outputs I2S or SPDIF
• Inputs I2S and SPDIF to output DAC.
Features:
SPDIF LOCK
XTAL
PLL
• BCK and WS of I2S output are master
MUTE
ADC
• Inputs SPDIF and I2S to output DAC
with mixing/selection possibility; clocks
are generated from SPDIF input signal,
and BCK and WS are master
DAC
SPDIF IN
SPDIF OUT
• SPDIF input channel status bits (two
times 40) can be read
2
2
2
2
I S slave
I S master
I S INPUT
I S OUTPUT
• SPDIF output channel status bits (two
MGU851
times 40) setting.
13
Data path:
• Input ADC to output I2S
• Inputs I2S and SPDIF to outputs DAC
SPDIF LOCK
XTAL
PLL
MUTE
or SPDIF.
ADC
Features
DAC
• BCK and WS being master
SPDIF IN
• SPDIF input channel status bits (two
times 40) can be read
SPDIF OUT
SPDIF
OUT
• Output SPDIF supported but the timing
not according to level II
2
2
I S master
I S OUTPUT
2
2
• Output SPDIFOUT loop through can
be selected with independent SPDIF
input channel select.
I S slave
I S INPUT
MGU852
14
Data path:
• Inputs ADC and I2S to outputs DAC
SPDIF and I2S.
2
I
S LOCK
PLL
Features:
ADC
MUTE
• All clocks are related to WS signal of
I2S-bus input
DAC
• Master BCK and WS for I2S output;
slave BCK and WS for I2S input
SPDIF OUT
• SPDIF output channel status bits (two
times 40) can be set; level II timing
depends on the I2S-bus clocks.
2
2
2
2
I S slave
I S master
I S INPUT
I S OUTPUT
MGU853
15
Not used
2003 Apr 10
30
NXP [ NXP ]
