Philips Semiconductors
Product specification
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
SCC2698B
clock is used instead of a crystal, X1 must be driven and X2 left
floating as shown in Figure 9. The clock serves as the basic timing
reference for the baud rate generator (BRG), the counter/timer, and
other internal circuits. A clock frequency, within the limits specified in
the electrical specifications, must be supplied even if the internal
BRG is not used.
Table 1.
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Register Addressing
Units A and B
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
READ (RDN=0)
MR1a, MR2a
SRa
BRG Test
2
RHRa
IPCRA
ISRA
CTUA
CTLA
MR1b, MR2b
SRb
1X/16X Test
2
RHRb
Reserved
1
Input port A
Start C/T A
Stop C/T A
WRITE
(WRN=0)
MR1a, MR2a
CSRa
CRa
THRa
ACRA
IMRA
CTPUA
CTPLA
MR1b, MR2b
CSRb
CRb
THRb
Reserved
1
OPCRA
Reserved
1
Reserved
1
A5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Units E and F
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
READ (RDN=0)
MR1e, MR2e
SRe
Reserved
1
RHRe
IPCRC
ISRC
CTUC
CTLC
MR1f, MR2f
SRf
Reserved
1
RHRf
Reserved
1
Input port C
Start C/T C
Stop C/T C
WRITE
(WRN=0)
MR1e, MR2e
CSRe
CRe
THRe
ACRC
IMRC
CTPUC
CTPLC
MR1f, MR2f
CSRf
CRf
THRf
Reserved
1
OPCRC
Reserved
1
Reserved
1
0
1
0
0
0
MR1c, MR2c
1
1
0
0
0
MR1g, MR2g
0
1
0
0
0
CSRc
1
1
0
0
0
CSRg
0
1
0
0
1
CRc
1
1
0
0
1
CRg
0
1
0
0
1
THRc
1
1
0
0
1
THRg
0
1
0
1
0
ACRB
1
1
0
1
0
ACRD
0
1
0
1
0
IMRB
1
1
0
1
0
IMRD
0
1
0
1
1
CTPUB
1
1
0
1
1
CTPUD
0
1
0
1
1
CTPLB
1
1
0
1
1
CTPLD
0
1
1
0
0
MR1d, MR2d
1
1
1
0
0
MR1h, MR2h
0
1
1
0
0
CSRd
1
1
1
0
0
CSRh
0
1
1
0
1
CRd
1
1
1
0
1
CRh
0
1
1
0
1
THRd
1
1
1
0
1
THRh
0
1
1
1
0
Reserved
1
1
1
1
1
0
Reserved
1
0
1
1
1
0
OPCRB
1
1
1
1
0
OPCRD
1
0
1
1
1
1
Reserved
1
1
1
1
1
Reserved
1
0
1
1
1
1
Reserved
1
1
1
1
1
1
Reserved
1
NOTE:
1. Reserved registers should never be read during normal operation since they are reserved for internal diagnostics.
ACR = Auxiliary control register
SR
= Status Register
CR
= Command register
THR = Tx holding register
CSR = Clock select register
RHR = Rx holding register
CTL = Counter/timer lower
IPCR = Input port change register
CTPL = Counter/timer preset lower register
ISR = Interrupt status register
CTU = Counter/timer upper
IMR = Interrupt mask register
CTPU = Counter/timer preset upper register
OPCR = Output port configuration register
MR = Mode register
2. See Table 5 for BRG Test frequencies in this data sheet, and
“Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681
and SCC2698B”
Philips Semiconductors ICs for Data Communications, IC-19, 1994.
Units C and D
0
MR1c, MR2c
1
SRc
0
Reserved
1
1
RHRc
0
IPCRB
1
ISRB
0
CTUB
1
CTLB
0
MR1d, MR2d
1
SRd
0
Reserved
1
1
RHRd
0
Reserved
1
1
Input port B
0
Start C/T B
1
Stop C/T B
Units G and H
0
MR1g, MR2g
1
SRg
0
Reserved
1
1
RHRg
0
IPCRD
1
ISRD
0
CTUD
1
CTLD
0
MR1h, MR2h
1
SRh
0
Reserved
1
1
RHRh
0
Reserved
1
1
Input port D
0
Start C/T D
1
Stop C/T D
BRG
The baud rate generator operates from the oscillator or external
clock input and is capable of generating 26 commonly used data
communications baud rates ranging from 50 to 115.2K baud.
Thirteen of these are available simultaneously for use by the
receiver and transmitter. Eight are fixed, and one of two sets of five
can be selected by programming ACR[7]. The clock outputs from
the BRG are at 16X the actual baud rate. The counter/timer can be
used as a timer to produce a 16X clock for any other baud rate by
counting down the crystal clock or an external clock. The clock
selectors allow the independent selection, by the receiver and
transmitter, of any of these baud rates or an external timing signal.
Counter–Timer
The four Counter/Timers are programmable 16 bit dividers that are
used for generating miscellaneous clocks or generating timeout
2000 Jan 31
7
PHILIPS [ NXP SEMICONDUCTORS ]
