Philips Semiconductors
Product specification
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
SCC2698B
Table 2. Register Bit Formats (Continued)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CSR (Clock Select Register)
Receiver Clock Select
Transmitter Clock Select
See text
See text
* See Table 5 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” Philips Semiconductors ICs for Data Communications, IC-19, 1994.
OPCR (Output Port Configuration Register) This register controls the MPP I/O pins and the MPO multi-purpose output pins.
MPP Function
Select
Power-Down
MPOb Pin Function Select
MPOa Pin Function Select
Mode*
0 = input
000 = RTSN
001 = C/TO
0 = Off
1 = On
000 = RTSN
001 = C/TO
1 = output
010 = TxC (1X)
011 = TxC (16X)
100 = RxC (1X)
101 = RxC (16X)
110 = TxRDY
010 = TxC (1X)
011 = TxC (16X)
100 = RxC (1X)
101 = RxC (16X)
110 = TxRDY
111 = RxRDY/FF
111 = RxRDY/FF
NOTE: *Only OPCR[3] in block A controls the power-down mode.
ACR (Auxiliary Control Register)
Delta
MPI1bINT
Delta
MPI0bINT
Delta
MPI1aINT
Delta
MPI0aINT
BRG Select
Counter/Timer Mode and Source
0 = set 1
1 = set 2
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
See Text
IPCR (Input Port Change Register)
Delta MPI1b
Delta MPI0b
Delta MPI1a
Delta MPI0a
MPI1b
MPI0b
MPI1a
MPI0a
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
ISR (Interrupt Status Register)
MPI Port
RxRDY/
FFULLb
Counter
Ready
RxRDY/
FFULLa
Delta BREAKb
Change
TxRDYb
Delta BREAKa
TxRDYa
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
IMR (Interrupt Mask Register)
MPI Port
Change INT
Delta BREAKb
INT
RxRDY/
FFULLb INT
Counter
Ready INT
Delta BREAKa
INT
RxRDY/
FFULLa INT
TxRDYb INT
TxRDYa INT
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
CTPU (Counter/Timer Upper Register)
C/T[15] C/T[14]
C/T[13]
C/T[5]
C/T[12]
C/T[4]
C/T[11]
C/T[3]
C/T[10]
C/T[2]
C/T[9]
C/T[1]
C/T[8]
C/T[0]
CTPU (Counter/Timer Lower Register)
C/T[7] C/T[6]
IPR (Input Port Register) MPP and MPI Pins
MPP2b
MPP1b
MPP2a
MPP1a
MPI1b
MPI0b
MPI1a
MPI0a
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
NOTE: When TxEMT and TxRDY bits are at one just before a write to the Transmit Holding register, a command to disable the transmitter
should be delayed until the TxRDY is at one again. TxRDY will set to one at the end of the start bit time.
14
2000 Jan 31
NXP [ NXP ]
