Philips Semiconductors
Product specification
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
SCC2698B
Table 2. Register Bit Formats
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MR1 (Mode Register 1)
RxRTS
RxINT Select
Error Mode*
Parity Mode
Parity Type
Bits per Character
Control
0 = No
0 = RxRDY
1 = FFULL
0 = Char
1 = Block
00 = With parity
01 = Force parity
10 = No parity
0 = Even
1 = Odd
00 = 5
01 = 6
10 = 7
11 = 8
1 = Yes
11 = Special mode
NOTE: *In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
MR2 (Mode Register 2)
TxRTS
Control
CTS Enable
Tx
Channel Mode
Stop Bit Length*
00 = Normal
01 = Auto-echo
10 = Local loop
11 = Remote loop
0 = 0.563 4 = 0.813 8 = 1.563 C = 1.813
1 = 0.625 5 = 0.875 9 = 1.625 C = 1.875
2 = 0.688 6 = 0.938 A = 1.688 E = 1.938
3 = 0.750 7 = 1.000 B = 1.750 F = 2.000
0 = No
0 = No
1 = Yes
1 = Yes
NOTE: *Add 0.5 to values shown above for 0–7, if channel is programmed for 5 bits/char.
CR (Command Register)
Miscellaneous Commands
Disable Tx
0 = No
Enable Tx
0 = No
Disable Rx
0 = No
Enable Rx
0 = No
See text
1 = Yes
1 = Yes
1 = Yes
1 = Yes
NOTE: Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. A disabled transmitter
cannot be loaded
SR (Status Register)
Framing
Rec’d Break*
Parity Error*
Overrun Error
TxEMT
TxRDY
FFULL
RxRDY
Error*
0 = No
1 = Yes
0 = No
0 = No
0 = No
0 = No
0 = No
0 = No
0 = No
1 = Yes
1 = Yes
1 = Yes
1 = Yes
1 = Yes
1 = Yes
1 = Yes
NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status register provides these
bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a reset error status command. In character mode, they
must be reset when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by
using the error reset command (command 4x) or a receiver reset.
13
2000 Jan 31
NXP [ NXP ]
