Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
AC ELECTRICAL CHARACTERISTICS FOR PHILIPS DEVICES
1, 2, 4, 5
T
amb
= 0°C to +70°C, V = 5V ±20%, V = 0V (PCB80C31/51, PCF80C31/51)
CC SS
3
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency: Speed Versions
MIN
MAX
UNIT
CLCL
PCB8031/51
–2
–3
–4
–5
0.5
1.2
1.2
1.2
12
16
24
33
MHz
MHz
MHz
MHz
PCA/PCB/PCF80C31/51
PCB/PCF80C31/51
PCB/FB80C31/51
t
t
t
t
t
t
t
t
t
t
t
1
1
1
1
1
1
1
1
1
1
1
ALE pulse width
2t
–40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
t
t
–25
AVLL
LLAX
LLIV
CLCL
CLCL
–25
4t
3t
–65
CLCL
t
–25
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
3t
CLCL
–45
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–60
CLCL
0
t
–25
CLCL
5t
CLCL
–80
10
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
RD pulse width
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
5t
2t
–90
–28
CLCL
0
Data float after RD
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
8t
–150
–165
CLCL
CLCL
9t
AVDV
LLWL
AVWL
QVWX
WHQX
RLAZ
WHLH
3t
–50
–75
3t
CLCL
+50
CLCL
4t
CLCL
t
t
–30
–25
CLCL
CLCL
RD low to address float
RD or WR high to ALE high
0
t
–25
t
+25
CLCL
CLCL
External Clock
t
t
t
t
5
5
5
5
High time
Low time
Rise time
Fall time
15
15
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
20
20
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. For all Philips speed versions only.
4. Interfacing the 80C31/51 to devices with float times up to 30ns is permitted. This limited bus contention will not cause damage to port 0
drivers.
5. V = 5V ±10% for 33MHz.
CC
14
1996 Aug 16
NXP [ NXP ]
