Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
DC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%; V = 0V
CC SS
LIMITS
TEST
CONDITIONS
SYMBOL
PARAMETER
UNIT
1
MIN
TYP
MAX
0.2V –0.1
V
V
V
Input low voltage
4.5V < V < 5.5V
–0.5
V
V
V
IL
CC
CC
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
0.2V +0.9
V
CC
V
CC
+0.5
+0.5
IH
CC
0.7V
IH1
CC
V
OL
= 4.5V
= 1.6mA
CC
8
V
V
V
V
Output low voltage, ports 1, 2, 3
0.4
V
V
V
OL
2
I
I
V
CC
= 4.5V
8, 7
Output low voltage, port 0, ALE, PSEN
0.4
OL1
OH
2
= 3.2mA
OL
V
CC
= 4.5V
= –30µA
3
Output high voltage, ports 1, 2, 3
V
V
– 0.7
– 0.7
CC
I
OH
Output high voltage (port 0 in external bus mode),
V
CC
= 4.5V
= –3.2mA
V
OH1
CC
9
3
ALE , PSEN
I
OH
I
I
Logical 0 input current, ports 1, 2, 3
V
V
= 0.4V
= 2.0V
–1
–50
–650
±10
µA
µA
µA
IL
IN
IN
6
Logical 1-to-0 transition current, ports 1, 2, 3
TL
See note 4
I
I
Input leakage current, port 0
0.45 < V < V – 0.3
LI
IN
CC
Power supply current (see Figure 8):
See note 5
CC
5
Active mode @ 16MHz
Idle mode @ 16MHz
11.5
1.3
3
32
5
50
µA
µA
µA
µA
5
Power-down mode
T
T
amb
= 0 to +70°C
amb
= –40 to +85°C
75
R
C
Internal reset pull-down resistor
40
225
15
kΩ
RST
IO
10
Pin capacitance (except EA)
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the (V –0.7) specification when the
OH
CC
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2V.
IN
5. See Figures 9 through 12 for I test conditions.
CC
Active Mode:
Idle Mode:
I
I
= 1.5 × FREQ + 8.0;
= 0.14 × FREQ +2.31; See Figure 8.
CC
CC
6. This value applies to T
= 0°C to +70°C. For T = –40°C to +85°C, I = –750µA.
amb TL
amb
7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
8. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
15mA (*NOTE: This is 85°C specification.)
OL
Maximum I per 8-bit port:
26mA
71mA
OL
Maximum total I for all outputs:
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
9. ALE is tested to V
, except when ALE is off then V is the voltage specification.
OH
OH1
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF
(except EA it is 25pF).
12
1996 Aug 16
NXP [ NXP ]
