Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 81 HPS, horizontal fine-scale
OFFSET
(HEX)
NAME
BIT
TYP.
DESCRIPTION
horizontal interpolation mode:
6C
XIM
31
RW
0: normal mode, sample phase is calculated for every qualified
sample
1: fixed phase, sample phase is fixed to the value set by XP
XP
30 to 24
23 to 12
RW
RW
start phase for horizontal fine scaling XP = PHOP × 128
(PHOP represents a phase offset with values between ‘0’ and ‘1’,
where the ‘1’ represents a distance between two consecutive
pixels of the input pattern)
XSCI
X Scaler Increment for fine (phase correct) scaling in
horizontal pixel phase arithmetic:
XSCI = INT [(NIP/NOP) × 1024/(SPSC + 1)]
NOP = number of output pixels
NIP = number of qualified scaler input pixels.
HXO
11 to 0
RW
horizontal offset (horizontal start) of input source for HPS, counted
in qualified pixels with PXQ, after selected horizontal sync edge.
7.12.7 BCS
Table 82 BCS control
OFFSET
NAME
(HEX)
BIT
TYPE
DESCRIPTION
70
BRIG
CONT
−
31 to 24
23 to 16
15 to 8
7 to 0
RW
RW
−
luminance brightness control; see Table 83
luminance contrast control; see Table 84
reserved
SATN
RW
chrominance saturation control; see Table 85
Table 83 Luminance brightness control
D7
D6
D5
D4
D3
D2
D1
D0
GAIN
255 (bright)
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
128 (CCIR level)
0 (dark)
Table 84 Luminance contrast control
D7
D6
D5
D4
D3
D2
D1
D0
GAIN
0
0
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1.999 (max. contrast)
1 (CCIR level)
0 (luminance off)
1998 Apr 09
94
NXP [ NXP ]
