Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Notes
1. Input leakage currents include high-impedance output leakage for all bidirectional buffer with 3-state outputs.
2. Levels measured with load circuit: 1.2 kΩ at 3 V (TTL load) and CL = 40 pF.
3. Voltage of the VDDI2C sense pin is defined as VDDI2C (4.75 : 5.0 : 5.25) (MIN. : TYP. : MAX.) for 5 V I2C-bus devices
and VDDI2C (3.0 : 3.3 : 3.6) (MIN. : TYP. : MAX.) for 3 V I2C-bus devices.
4. Cb = capacitance of one bus line measured in pF.
5. I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VDDI2C is switched off.
6. FRAME#, TRDY#, IRDY#, DEVSEL# and STOP#.
7. Lower capacitance on this input only pin allows for non-resistive coupling to AD(xx).
8. Refer to the V/I curves in PCI specification. ‘Switching current high’ specifications are not relevant to INTA#, which
are open-drain outputs.
9. IOH = 11.9 × (Vo − 5.25) × (Vo + 2.45) for VDDD > Vo > 3.1 V.
10. IOL = 78.5 × Vo × (4.4 − Vo) for 0 V < Vo < 0.71 V.
11. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the
instantaneous rate at any point within the transition range.
12. REQ# and GNT# are point-to-point signals, and have different output valid delay and input set-up times that do
bussed signals. GNT# has a set-up time of 10 ns. REQ# has an output valid delay time of 12 ns. All other signals are
bussed.
13. For purposes of active/float timing measurements the high-impedance or ‘off’ state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification.
14. RST# is asserted and de-asserted asynchronously with respect to CLK.
15. All output drivers floated asynchronously when RST# is active.
1998 Apr 09
136
NXP [ NXP ]
