Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
OFFSET
(HEX)
READ VALUE
AFTER RESET
NAME
TYPE RAM
CORRESPONDING UPLOAD BIT
88
7C
80
DEBI_AD
RW
RW
RW
RW
RW
RW
RW
RW
R
yes
yes
yes
yes
read
read
no
undefined
undefined
undefined
undefined
undefined
undefined
00000000
00000000
00000000
no read back
no read back
DEBI upload
DEBI_CONFIG
DEBI_COMMAND
DEBI_PAGE
ACON1
84
F4
immediate write access
immediate access
F8
ACON2
144
148
140
FB_BUFFER1
FB_BUFFER2
LEVEL_REP
no
no
−
180-1BC audio time slot registers 1
1C0-1FC audio time slot registers 2
W
no
immediate access
W
no
Table 115 Registers and offsets sorted by address-offset
OFFSET
(HEX)
READ VALUE
AFTER RESET
NAME
TYPE RAM
CORRESPONDING UPLOAD BIT
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
BaseOdd1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
read
yes
yes
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
video DMA1 upload
BaseEven1
ProtAddr1
Pitch1
BasePage1
Num_Line_Byte1
BaseOdd2
video DMA2 upload
BaseEven2
ProtAddr2
Pitch2
BasePage2
Num_Line_Byte2
BaseOdd3
video DMA3 upload
BaseEven3
ProtAddr3
Pitch3
BasePage3
Num_Line_Byte3
PCI_BT_V
video DMA 1 2 or 3 upload
immediate write access
D1 Interface upload
PCI_BT_A
initial settings DD1 port
video DATA stream handling
at port DD1
58
BRS control register
HPS control
RW
RW
yes
yes
undefined
undefined
BRS upload
5C
HPS section 1 upload
1998 Apr 09
129
NXP [ NXP ]
