SAA7113H
Philips Semiconductors
9-bit video input processor
Table 37: Luminance control subaddress 09h (D7 to D0) …continued
Function
Control bit
APER1
Logic level Data bit
Aperture factor = 0.5
1
0
1
1
D1
D0
D1
D0
APER0
Aperture factor = 1.0
APER1
APER0
Update time interval for analog AGC value (UPTCV)
Horizontal update (once per line)
UPTCV
UPTCV
0
1
D2
D2
Vertical update (once per field)
Vertical blanking luminance bypass (VBLB)
Active luminance processing
VBLB
VBLB
0
1
D3
D3
Chrominance trap and peaking stage are disabled
during VBI lines determined by VREF = 0 (see Table 46)
Aperture band-pass (center frequency) (BPSS)
Center frequency = 4.1 MHz
BPSS1
BPSS0
BPSS1
BPSS0
BPSS1
BPSS0
BPSS1
BPSS0
0
0
0
1
1
0
1
1
D5
D4
D5
D4
D5
D4
D5
D4
Center frequency = 3.8 MHz[1]
Center frequency = 2.6 MHz[1]
Center frequency = 2.9 MHz[1]
Prefilter active (PREF); see Figure 11, Figure 12, Figure 14, Figure 16 and Figure 17
Bypassed
PREF
PREF
0
1
D6
D6
Active
Chrominance trap bypass (BYPS)
Chrominance trap active; default for CVBS mode
Chrominance trap bypassed; default for S-video mode
BYPS
BYPS
0
1
D7
D7
[1] Not to be used with bypassed chrominance trap.
9.2.11 Subaddress 0Ah
Table 38: Luminance brightness control subaddress 0Ah (D7 to D0)
Offset
Control bits D7 to D0
BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0
255 (bright)
128 (ITU level)
0 (dark)
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
42 of 75
NXP [ NXP ]
