SAA7113H
Philips Semiconductors
9-bit video input processor
9.2.18 Subaddress 11h
Table 49: Output control 1 subaddress 11h
Function
Bit
Logic level Data bit
Color on (COLO)
Automatic color killer
COLO
COLO
0
1
D0
D0
Color forced on
YUV decoder bypassed (VIPB)
Processed data to VPO output
ADC data to VPO output; dependent on mode settings
Output enable real-time (OERT)
RTS0, RTS1, RTCO high-impedance inputs
VIPB
VIPB
0
1
D1
D1
OERT
OERT
0
1
D2
D2
RTS0, RTCO active, RTS1 active, if RTSE13 to
RTSE10 = 0000
Output enable YUV data (OEYC)
VPO-bus high-impedance
OEYC
OEYC
0
1
D3
D3
Output VPO-bus active or controlled by RTS1
(see Table 22)
Selection of horizontal lock indicator for RTS0 and RTS1 outputs
Standard horizontal lock indicator (low-passed)
HLSEL
HLSEL
0
1
D4
D4
Fast lock indicator (use is recommended only for high
performance input signals)
General purpose switch [available on pin RTS0, if control bits RTSE03 to RTSE00
(subaddress 12h) is set to 0010]
LOW
GPSW0
GPSW0
0
1
D5
D5
HIGH
CM99 compatibility to SAA7199 (CM99)
Default value
CM99
CM99
0
1
D6
D6
To be set only if SAA7199 (digital encoder) is used for
re-encoding in conjunction with RTCO
General purpose switch [available on pin RTS1, if control bits RTSE13 to RTSE10
(subaddress 12h) is set to 0010]
LOW
GPSW1
GPSW1
0
1
D7
D7
HIGH
9.2.19 Subaddress 12h
Table 50: RTS0 output control subaddress 12h
RTS0 output control
Control bits D3 to D0
RTSE03 RTSE02 RTSE01 RTSE00
Reserved
0
0
0
0
0
0
0
1
VIPB (subaddress 11h, bit 1) = 0: reserved
VIPB (subaddress 11h, bit 1) = 1: LSBs of the 9-bit ADCs
GPSW0 level (subaddress 11h, bit 5)
0
0
1
0
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
46 of 75
NXP [ NXP ]
