SAA7113H
Philips Semiconductors
9-bit video input processor
Table 42: Chrominance control subaddress 0Eh …continued
Function
50 Hz
Control bit
Logic
level
Data bit
60 Hz
Fast color time constant (FCTC)
Nominal time constant
FCTC
FCTC
0
1
D2
D2
Fast time constant
Disable chrominance comb filter (DCCF)
Chrominance comb filter on (during lines determined by
VREF = 1; see Table 46)
DCCF
DCCF
0
1
D3
D3
Chrominance comb filter permanently off
Color standard selection (CSTD0 to CSTD2); logic levels 100, 110 and 111 are reserved, do
not use
PAL BGHIN
NTSC M (or NTSC-Japan with
special level adjustment:
brightness subaddress 0Ah = 95h;
contrast subaddress 0Bh = 48h)
CSTD2
CSTD1
CSTD0
0
0
0
D6
D5
D4
NTSC 4.43 (50 Hz)
Combination-PAL N
NTSC N
PAL 4.43 (60 Hz)
NTSC 4.43 (60 Hz)
PAL M
CSTD2
CSTD1
CSTD0
CSTD2
CSTD1
CSTD0
CSTD2
CSTD1
CSTD0
CSTD2
CSTD1
CSTD0
0
0
1
0
1
0
0
1
1
1
0
1
D6
D5
D4
D6
D5
D4
D6
D5
D4
D6
D5
D4
SECAM
reserved
Clear DTO (CDTO)
Disabled
CDTO
0
1
D7
D7
Every time CDTO is set, the internal subcarrier DTO phase CDTO
is reset to 0° and the RTCO output generates a logic 0 at
time slot 68 (see external document “RTC Functional
Description”, available on request). So an identical
subcarrier phase can be generated by an external device
(e.g. an encoder).
9.2.16 Subaddress 0Fh
Table 43: Chrominance gain control subaddress 0Fh (D6 to D0)
Chrominance gain
value (if ACGC is set
to logic 1)
Control bits D6 to D0
CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0
Minimum gain (0.5)
Nominal gain (1.125)
Maximum gain (7.5)
0
0
1
0
1
1
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
44 of 75
NXP [ NXP ]
