Philips Semiconductors
Product specification
Radio tuning PLL frequency synthesizer
SAA1057
CHARACTERISTICS
VEE = 0 V; VCC1 = VCC2 = 5 V; VCC3 = 30 V; Tamb = 25 °C; unless otherwise specified
SYMBOL
VCC1
MIN.
3,6
TYP.
MAX.
CONDITIONS
Supply voltages
5
12
12
31
V
V
V
VCC2
3,6
5
VCC3
VCC2
−
Supply currents(6)
AM mode
Itot
−
16
20
0,8
−
mA
mA
mA
I
tot = ICC1 + ICC2 in-lock:
BRM = ‘1’; PDM = ‘0’
FM mode
Itot
−
−
ICC3
0,3
1,2
IOUT = 0
Operating ambient
temperature
Tamb
−25
−
+80
°C
RF inputs (FAM, FFM)
AM input frequency
fFAM
fFFM
Vi (rms)
Vi (rms)
Ri
512 kHz
−
32
120
500
500
−
MHz
MHz
mV
mV
kΩ
FM input frequency
70
30
10
−
−
Input voltage at FAM
Input voltage at FFM
Input resistance at FAM
Input resistance at FFM
Input capacitance at FAM
Input capacitance at FFM
Voltage ratio allowed
between selected and
non-selected input
−
−
2
Ri
−
135
3,5
3
−
Ω
Ci
−
−
pF
Ci
−
−
pF
Vs/Vns
−
−30
−
dB
see note 1
Crystal oscillator (XTAL)
Maximum input frequency
Crystal series resistance
fXTAL
Rs
4
−
−
−
MHz
−
150
Ω
BUS inputs (DLEN, CLB, DATA)
Input voltage LOW
VIL
VIH
−IIL
IIH
0
−
−
−
−
0,8
VCC1
10
V
Input voltage HIGH
2,4
−
V
Input current LOW
µA
µA
VIL = 0,8 V
Input current HIGH
−
10
VIH = 2,4 V
see also Fig.2 and
BUS inputs timing
(DLEN, CLB, DATA)
Lead time for CLB to DLEN
Lead time for DATA to
the first CLB pulse
Set-up time for DLEN
to CLB
note 2
tCLBlead
1
−
−
−
−
µs
µs
tTlead
0,5
tCLBlag1
tCLBH
5
5
5
−
−
−
−
−
−
µs
µs
µs
CLB pulse width HIGH
CLB pulse width LOW
tCLBL
November 1983
7
NXP [ NXP ]
