Philips Semiconductors
Product specification
Radio tuning PLL frequency synthesizer
SAA1057
Fig.1 Block diagram.
• A reference frequency oscillator followed by a reference
divider. The frequency is generated by a 4 MHz quartz
crystal. The reference frequency can be chosen either
32 kHz or 40 kHz for the digital phase detector (that
means 1 kHz and 1,25 kHz for the sample and hold
phase detector), which results in tuning steps of 1 kHz
and 1,25 kHz for AM, and 10 kHz and 12,5 kHz for FM.
GENERAL DESCRIPTION
The SAA1057 performs the entire PLL synthesizer
function (from frequency inputs to tuning voltage output)
for all types of radios with the AM and FM frequency
ranges.
The circuit comprises the following:
• A programmable current amplifier (charge pump), which
controls the output current of both the digital and the
sample/hold phase detector in a range of 40 dB. It also
allows the loop gain of the tuning system to be adjusted
by the microcomputer.
• Separate input amplifiers for the AM and FM
VCO-signals.
• A divider-by-10 for the FM channel.
• A multiplexer which selects the AM or FM input.
• A 15-bit programmable divider for selecting the required
frequency.
• A tuning voltage amplifier, which can deliver a tuning
voltage of up to 30 V.
• A sample and hold phase detector for the in-lock
condition, to achieve the high spectral purity of the VCO
signal.
• BUS; this circuitry consists of a format control part, a
16-bit shift register and two 15-bit latches. Latch A
contains the to be tuned frequency information in a
binary code. This binary-coded number, multiplied by
the tuning spacing, is equal to the synthesized
frequency. The programmable divider (without the fixed
divide-by-10 prescaler for FM) can be programmed in a
range between 512 and 32 767 (see Fig.3). Latch B
contains the control information.
• A digital memory frequency/phase detector, which
operates at a 32 times higher frequency than the sample
and hold phase detector, so fast tuning can be achieved.
• An in-lock counter detects when the system is in-lock.
The digital phase detector is switched-off automatically
when an in-lock condition is detected.
November 1983
3
NXP [ NXP ]
