PDIUSBD12
USB interface device with parallel bus
Rev. 08 — 20 December 2001
Product data
1. Description
The PDIUSBD12 is a cost and feature optimized USB device. It is normally used in
microcontroller based systems and communicates with the system microcontroller
over the high-speed general purpose parallel interface. It also supports local DMA
transfer.
This modular approach to implementing a USB interface allows the designer to
choose the optimum system microcontroller from the available wide variety. This
flexibility cuts down the development time, risks, and costs by allowing the use of the
existing architecture and minimize firmware investments. This results in the fastest
way to develop the most cost effective USB peripheral solution.
The PDIUSBD12 fully conforms to the USB specification Rev. 2.0 (basic speed). It is
also designed to be compliant with most device class specifications: Imaging Class,
Mass Storage Devices, Communication Devices, Printing Devices, and Human
Interface Devices. As such, the PDIUSBD12 is ideally suited for many peripherals like
Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers
an immediate cost reduction for applications that currently use SCSI
implementations.
The PDIUSBD12 low suspend power consumption along with the LazyClock output
allows for easy implementation of equipment that is compliant to the ACPI™,
OnNOW™, and USB power management requirements. The low operating power
allows the implementation of bus powered peripherals.
In addition, it also incorporates features like SoftConnect™, GoodLink™,
programmable clock output, low frequency crystal oscillator, and integration of
termination resistors. All of these features contribute to significant cost savings in the
system implementation and at the same time ease the implementation of advanced
USB functionality into the peripherals.
2. Features
■ Complies with the Universal Serial Bus specification Rev. 2.0 (basic speed)
■ High performance USB interface device with integrated SIE, FIFO memory,
transceiver and voltage regulator
■ Compliant with most Device Class specifications
■ High-speed (2 Mbytes/s) parallel interface to any external microcontroller or
microprocessor
■ Fully autonomous DMA operation
■ Integrated 320 bytes of multi-configuration FIFO memory
NXP [ NXP ]
