PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
• A master receiver must signal an end-of-data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
master receiver must leave the data line HIGH during the 9th pulse to not
acknowledge. The master will now generate a STOP condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 15. Acknowledgement on the I2C-bus
8.1.4 PCF8566 I2C-bus controller
The PCF8566 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8566 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, the transferred command data and the hardware subaddress.
In single device application, the hardware subaddress inputs A0, A1 and A2 are normally
tied to VSS which defines the hardware subaddress 0. In multiple device applications
A0, A1 and A2 are tied to VSS or VDD using a binary coding scheme so that no two
devices with a common I2C-bus slave address have the same hardware subaddress.
In the power-saving mode it is possible that the PCF8566 is not able to keep up with the
highest transmission rates when large amounts of display data are transmitted. If this
situation occurs, the PCF8566 forces the SCL line LOW until its internal operations are
completed. This is known as the clock synchronization feature of the I2C-bus and serves
to slow down fast transmitters. Data loss does not occur.
8.1.5 Input filter
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.2 I2C-bus protocol
Two I2C-bus 7 bit slave addresses (0111 110 and 0111 111) are reserved for the
PCF8566. The least significant bit after the slave address is bit R/W. The PCF8566 is a
write-only device. It will not respond to a read access, so this bit should always be logic 0.
The second bit of the slave address is defined by the level tied at input SA0.
PCF8566_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2009
22 of 48
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