PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
R/W
slave address
S
A
0
0
1
1
1
1
1
0
1 byte
001aai455
Fig 16. Slave address structure
Two displays controlled by PCF8566 can be recognized on the same I2C-bus which
allows:
• Up to 16 PCF8566s on the same I2C-bus for very large LCD applications (see
Section 13)
• The use of two types of LCD multiplex on the same I2C-bus
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the PCF8566 slave
addresses. All PCF8566s with the same SA0 level acknowledge in parallel to the slave
address. All PCF8566s with the alternative SA0 level ignore the whole I2C-bus transfer.
After acknowledgement, one or more command bytes (m) follow which define the status of
the addressed PCF8566s. The last command byte is tagged with a cleared most
significant bit, the continuation bit C. The command bytes are also acknowledged by all
addressed PCF8566s on the bus.
After the last command byte, a series of display data bytes (n) may follow. These display
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data is directed to the intended PCF8566 device.
The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed
PCF8566. After the last display byte, the I2C-bus master issues a STOP condition (P).
acknowledge
acknowledge by
by A0, A1 and A2
all addressed
selected
PCF8566 only
R/W
0
PCF8566s
slave address
S
A
0
S
0
1
1
1
1
1
A C
A
DISPLAY DATA
n > 0 byte(s)
A P
COMMAND
1 byte
m ≥ 1 byte(s)
update data pointers
and if necessary,
subaddress counter
mgg390
Fig 17. I2C-bus protocol
PCF8566_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2009
23 of 48
NXP [ NXP ]
