PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
8.3.5 Blink command
Table 16. Blink frequency command bit description
Blink frequency
Bit
BF1
0
BF0
0
off
1
0
1
2
1
0
3
1
1
Table 17. Blink mode command bit description
Blink mode
Bit A
Normal blinking
0
1
Alternate RAM bank blinking
8.4 Display controller
The display controller executes the commands identified by the command decoder. It
contains the status registers of the PCF8566 and coordinates their effects. The controller
also loads display data into the display RAM as required by the storage order.
9. Internal circuitry
V
LCD
V
SS
BP0 to BP3,
S0 to S23
SDA, SCL, SYNC,
CLK, OSC, A0 to A2,
SA0
V
DD
001aai456
Fig 19. Device protection diagram
PCF8566_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2009
26 of 48
NXP [ NXP ]
