PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 7.
Blink frequencies
Blinking mode
Normal operating
mode ratio
Power saving mode
ratio
Blink frequency
off
1
-
-
blinking off
2 Hz
f clk
f elk
f blink
f blink
f blink
=
=
=
f blink
f blink
f blink
=
=
=
----------------
92160
----------------
15360
2
3
1 Hz
f clk
f clk
-------------------
184320
----------------
30720
0.5 Hz
f clk
f clk
-------------------
368640
----------------
61440
An additional feature is for an arbitrary selection of LCD segments to be blinked. This
applies to the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. Using the output bank selector, the displayed RAM banks are
exchanged with alternate RAM banks at the blinking frequency. This mode can also be
specified by the blink select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can be blinked by selectively changing the display RAM data at fixed time
intervals.
If the entire display needs to be blinked at a frequency other than the nominal blinking
frequency, this can be done using the mode set command to set and reset the display
enable bit E at the required rate (see Table 9).
8. Basic architecture
8.1 Characteristics of the I2C-bus
The I2C-bus provides bidirectional, two-line communication between different IC or
modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When
connected to the output stages of a device, both lines must be connected to a positive
supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.
8.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse. Changes in the data line at this time will
be interpreted as a control signal. Bit transfer is illustrated in Figure 12.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 12. Bit transfer
PCF8566_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2009
20 of 48
NXP [ NXP ]
