PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
slave address
command byte
(cont.)
SDA
S
0
0
1
1
A2 A1 A0
0
A
A
START condition
R/W
acknowledge
from slave
acknowledge
from slave
slave address
data from register
DATA (first byte)
data from register
(cont.)
S
0
0
1
1
A2 A1 A0
1
A
A
DATA (last byte)
NA P
(repeated)
START condition
R/W
acknowledge
from master
no acknowledge STOP
from master condition
acknowledge
from slave
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
002aad283
Fig 16. Read from register
no acknowledge
from master
slave address
A2 A1 A0
data from port
DATA 1
data from port
DATA 4
SDA
S
0
0
1
1
1
A
A
NA
P
START condition
R/W acknowledge
from slave
acknowledge
from master
STOP
condition
read from
port
t
t
su(D)
h(D)
data into
port
DATA 1
DATA 2
DATA 3
DATA 4
002aad284
Remark: This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge
phase is valid (output mode). Input data is lost.
Fig 17. Read input port register
PCA9557
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 10 December 2013
12 of 30
NXP [ NXP ]
