Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
P87C552
AUXR
Address = 8EH
Not Bit Addressable
—
Bit:
7
—
6
—
5
—
4
—
3
LVADC
2
–
1
AO
0
Reset Value = xxxx x110B
Symbol
AO
Function
Disable/Enable ALE
AO
Operating Mode
0
ALE is emitted at a constant rate of 1/6 the oscillator frequency.
1
ALE is active only during a MOVX or MOVC instruction.
Enable A/D low voltage operation
LVADC
0
1
Operating Mode
Turns off A/D charge pump.
Turns on A/D charge pump. Required for operation below 4V.
LVADC
—
Not implemented, reserved for future use*.
NOTE:
*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that
case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01115
Figure 4. AUXR: Auxiliary Register
Dual DPTR
The dual DPTR structure (see Figure 5) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS = AUXR1/bit0 that allows the program
code to switch between them.
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
Note that bit 2 is not writable and is always read as a zero. This
allows the DPS bit to be quickly toggled simply by executing an
INC AUXR1 instruction without affecting the other bits.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR
MOV DPTR, #data16
Increments the data pointer by 1
Loads the DPTR with a 16-bit constant
Move code byte relative to DPTR to ACC
Move external RAM (16-bit address) to
ACC
Move ACC to external RAM (16-bit
address)
Jump indirect relative to DPTR
DPS
BIT0
AUXR1
MOV A, @ A+DPTR
MOVX A, @ DPTR
DPTR1
DPTR0
DPH
(83H)
DPL
(82H)
EXTERNAL
DATA
MEMORY
MOVX @ DPTR , A
JMP @ A + DPTR
SU00745A
Figure 5.
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
1999 Mar 30
11
PHILIPS [ NXP SEMICONDUCTORS ]
