ISP1581
USB 2.0 HS interface device
Philips Semiconductors
Table 13: Interrupt Enable register: bit description
Bit
Symbol
Description
31 to 26
25 to 12
-
reserved; must write logic 0
IEP7TX to
IEP1RX
A logic 1 enables interrupt from the indicated endpoint.
11
10
9
IEP0TX
IEP0RX
-
A logic 1 enables interrupt from the Control IN endpoint 0.
A logic 1 enables interrupt from the Control OUT endpoint 0.
reserved
8
IEP0SETUP
A logic 1 enables the interrupt for the Setup data received on
endpoint 0.
7
6
5
-
reserved
IEDMA
A logic 1 enables interrupt upon DMA status change detection.
IEHS_STA
A logic 1 enables interrupt upon detection of a High Speed
Status change.
4
3
2
1
0
IERESM
IESUSP
IEPSOF
IESOF
A logic 1 enables interrupt upon detection of a ‘resume’ state.
A logic 1 enables interrupt upon detection of a ‘suspend’ state.
A logic 1 enables interrupt upon detection of a Pseudo SOF.
A logic 1 enables interrupt upon detection of an SOF.
IEBRST
A logic 1 enables interrupt upon detection of a bus reset.
9.2.5 DMA Configuration register (address: 38H)
See Section 9.4.3.
9.2.6 DMA Hardware register (address: 3CH)
See Section 9.4.4.
9397 750 07648
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 02 — 23 October 2000
17 of 73
NXP [ NXP ]
