ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
(2)
DREQ
t
t
T
cy1
t
su1
w1
h1
(1)
(1)
DACK
t
t
w2
t
d2
d1
HIGH
DIOR/DIOW
t
h2
[
]
]
(read) DATA 15:0
t
t
su2
h3
[
(write) DATA 15:0
MGT501
DREQ is continuously asserted until the last transfer is done or the FIFO is full.
Data strobe: DACK (read/write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 22. GDMA slave mode timing (BURST = 00H, MODE = 02H).
(2)
DREQ
t
su1
t
t
t
h1
T
d1
w1
cy1
t
su3
(1)
(1)
DACK
t
t
a1
d2
DIOR/DIOW
t
h2
[
]
]
(read) DATA 15:0
t
t
h3
su2
[
(write) DATA 15:0
MGT502
DREQ is asserted for every transfer.
Data strobes: DIOR (read), DIOW (write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 23. GDMA slave mode timing (BURST = 01H, MODE = 00H).
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
62 of 79
NXP [ NXP ]
