ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
14.2 DMA timing
14.2.1 PIO mode
T
cy1
(1)
device
address
valid
t
t
su1
h1
(4)
DIOR, DIOW
t
t
w2
w1
(2)
(2)
[
]
(write) DATA 7:0
t
t
h2
su2
t
[
]
(read) DATA 7:0
t
h3(min)
su3
t
d2
HIGH
(3a)
IORDY
t
t
su4
su4
(3b)
(3c)
IORDY
IORDY
t
su5
MGT499
t
w3
(1) The device address consists of signals CS1, CS0, DA2, DA1 and DA0.
(2) The data bus width depends on the PIO access command used. Task File register access uses 8 bits (DATA[7:0]), except
for Task File register 1F0 which uses 16 bits (DATA[15:0]). DMA commands 04H and 05H also use a 16-bit data bus.
(3) The device can negate IORDY to extend the PIO cycle with wait states. The host determines whether or not to extend the
current cycle after tsu4 following the assertion of DIOR or DIOW. The following three cases are distinguished:
a). Device keeps IORDY released (high-impedance): no wait state is generated.
b). Device negates IORDY during tsu4, but re-asserts IORDY before tsu4 expires: no wait state is generated.
c). Device negates IORDY during tsu4 and keeps IORDY negated for at least 5 ns after tsu4 expires: a wait state is
generated. The cycle is completed as soon as IORDY is re-asserted. For extended read cycles (DIOR asserted), the read
data on lines DATAn must be valid at td1 before IORDY is asserted.
(4) DIOR and DIOW have a programmable polarity: shown here as active LOW signals.
Fig 20. PIO mode timing.
Table 77: PIO mode timing parameters
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = −40 to +85 °C.
Symbol Parameter
Tcy1(min) read/write cycle time (minimum)
tsu1(min)
Mode 0
600
Mode 1
383
Mode 2
240
Mode 3
180
Mode 4
120
Unit
ns
[1]
address to DIOR/DIOW on set-up time
(minimum)
70
50
30
30
25
ns
[1]
[1]
tw1(min)
tw2(min)
tsu2(min)
DIOR/DIOW pulse width (minimum)
DIOR/DIOW recovery time (minimum)
165
-
125
-
100
-
80
70
30
70
25
20
ns
ns
ns
data set-up time before DIOW off
(minimum)
60
45
30
th2(min)
data hold time after DIOW off (minimum)
30
20
15
10
10
ns
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
60 of 79
NXP [ NXP ]
