ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Table 52: HcFmNumber register: bit description
Bit
Symbol
−
Description
31 to 16
15 to 0
reserved
FN[15:0]
FrameNumber: This is incremented when HcFmRemaining is
reloaded. It needs to be rolled over to 0H after FFFFH. When the
USBOperational state is entered, this is incremented automatically.
The content needs to be written to HCCA after the HC has
incremented the FrameNumber (FN) at each frame boundary and
sent an SOF. However, the content needs to be written before
the HC reads the first Endpoint Descriptor (ED) in that frame. After
writing to HCCA, the HC needs to set the StartofFrame (SF) in
HcInterruptStatus.
15.2.4 HcLSThreshold register (R/W: 11H/91H)
The HcLSThreshold register contains an 11-bit value used by the HC to determine
whether to commit to the transfer of a maximum of 8-byte LS packet before the EOF.
Neither the HC nor the HCD is allowed to change this value. Table 53 shows the bit
allocation of the register.
Code (Hex): 11 — read
Code (Hex): 91 — write
Table 53: HcLSThreshold register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
Reset
Access
Bit
reserved
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
Symbol
Reset
Access
Bit
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Symbol
Reset
Access
Bit
reserved
LST[10:8]
-
-
-
-
-
-
-
-
-
-
1
R/W
2
1
R/W
1
0
R/W
0
7
6
5
4
3
Symbol
Reset
Access
LST[7:0]
0
0
1
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 54: HcLSThreshold register: bit description
Bit
Symbol
−
Description
31 to 11
10 to 0
reserved
LST[10:0]
LSThreshold: Contains a value that is compared to the
FrameRemaining (FR) field before a low-speed transaction is
initiated. The transaction is started only if FrameRemaining
(FR) ≥ this field. The value is calculated by the HCD, which
considers transmission and set-up overhead.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
81 of 150
NXP [ NXP ]
