ISP1362
Single-chip USB OTG controller
Philips Semiconductors
writing logic 0 to a bit in this register leaves the corresponding bit in the
HcInterruptEnable register unchanged. On a read, the current value of the
HcInterruptEnable register is returned. Table 45 provides the bit allocation of the
HcInterruptDisable register.
Code (Hex): 05 — read
Code (Hex): 85 — write
Table 45: HcInterruptDisable register: bit allocation
Bit
31
MIE
0
30
29
28
27
26
25
24
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
23
22
21
20
19
18
17
16
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
-
7
5
4
3
2
1
0
Symbol
Reset
Access
reserved
RHSC
0
FNO
0
UE
0
RD
0
SF
0
reserved
SO
0
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Table 46: HcInterruptDisable register: bit description
Bit
Symbol
Description
31
MIE
Logic 0 is ignored by the HC. Logic 1 disables interrupt generation
because of events specified in other bits of this register. This field
is set after a hardware or software reset.
30 to 7
6
-
reserved
RHSC
0 — ignore
1 — disable interrupt generation because of Root Hub Status
Change
5
FNO
0 — ignore
1 — disable interrupt generation because of Frame Number
Overflow
4
3
UE
RD
0 — ignore
1 — disable interrupt generation because of Unrecoverable Error
0 — ignore
1 — disable interrupt generation because of Resume Detect
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
77 of 150
NXP [ NXP ]
