ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Table 46: HcInterruptDisable register: bit description…continued
Bit
Symbol
Description
2
SF
0 — ignore
1 — disable interrupt generation because of Start of Frame
1
0
-
reserved
SO
0 — ignore
1 — disable interrupt generation because of Scheduling Overrun
15.2 HC Frame Counter registers
15.2.1 HcFmInterval register (R/W: 0DH/8DH)
The HcFmInterval register (bit allocation: Table 47) contains a 14-bit value that
indicates the bit time interval in a frame between two consecutive SOFs. In addition, it
contains a 15-bit value indicating the full-speed maximum packet size that the HC
may transmit or receive without causing a scheduling overrun. The HCD may carry
out minor adjustments on FrameInterval by writing a new value over the present one
at each SOF. This provides the programmability necessary for the HC to synchronize
with an external clocking resource and to adjust any unknown local clock offset.
Code (Hex): 0D — read
Code (Hex): 8D — write
Table 47: HcFmInterval register: bit allocation
Bit
31
FIT
0
30
29
28
27
26
25
24
Symbol
Reset
Access
Bit
FSMPS[14:8]
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
Symbol
Reset
Access
Bit
FSMPS[7:0]
0
0
0
0
0
0
0
R/W
9
0
R/W
8
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
Symbol
Reset
Access
Bit
reserved
FI[13:8]
-
-
-
-
1
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
7
6
Symbol
Reset
Access
FI[7:0]
1
1
0
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
78 of 150
NXP [ NXP ]
