ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Table 48: HcFmInterval register: bit description
Bit
Symbol
Description
31
FIT
FrameIntervalToggle: The HCD toggles this bit whenever it loads
a new value to FrameInterval.
30 to 16
FSMPS
[14:0]
FSLargestDataPacket: Specifies a value that is loaded into the
Largest Data Packet Counter at the beginning of each frame. The
counter value represents the largest amount of data in bits that can
be sent or received by the HC in a single transaction at any given
time without causing a scheduling overrun. The field value is
calculated by the HCD.
15 to 14
13 to 0
-
reserved
FI[13:0]
FrameInterval: Specifies the interval between two consecutive
SOFs in bit times. The nominal value is set to 11999. The HCD
must store the current value of this field before resetting the HC.
Setting the HostControllerReset (HCR) field of the
HcCommandStatus register causes the HC to reset this field to its
nominal value. The HCD may choose to restore the stored value
upon completing the Reset sequence.
15.2.2 HcFmRemaining register (R/W: 0EH/8EH)
The HcFmRemaining register is a 14-bit down counter showing the bit time remaining
in the current frame. The bit allocation is given in Table 49.
Code (Hex): 0E — read
Code (Hex): 8E — write
Table 49: HcFmRemaining register: bit allocation
Bit
31
FRT
0
30
29
28
27
26
25
24
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
23
22
21
20
19
18
17
16
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Symbol
Reset
Access
Bit
reserved
FR[13:8]
-
-
-
-
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
7
6
Symbol
Reset
Access
FR[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
79 of 150
NXP [ NXP ]
