ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Table 43: HcInterruptEnable register: bit allocation
Bit
31
MIE
0
30
29
28
27
26
25
24
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
23
22
21
20
19
18
17
16
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
-
7
5
4
3
2
1
0
Symbol
Reset
Access
reserved
RHSC
0
FNO
0
UE
0
RD
0
SF
0
reserved
SO
0
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Table 44: HcInterruptEnable register: bit description
Bit
Symbol
Description
31
MIE
MasterInterruptEnable by the HCD: Logic 0 is ignored by the HC.
Logic 1 enables interrupt generation by events specified in other
bits of this register.
30 to 7
6
-
reserved
RHSC
0 — ignore
1 — enable interrupt generation because of Root Hub Status
Change
5
FNO
0 — ignore
1 — enable interrupt generation because of Frame Number
Overflow
4
3
2
UE
RD
SF
0 — ignore
1 — enable interrupt generation because of Unrecoverable Error
0 — ignore
1 — enable interrupt generation because of Resume Detect
0 — ignore
1 — enable interrupt generation because of Start of Frame
1
0
-
reserved
SO
0 — ignore
1 — enable interrupt generation because of Scheduling Overrun
15.1.6 HcInterruptDisable register (R/W: 05H/85H)
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
76 of 150
NXP [ NXP ]
