ISP1362
Single-chip USB OTG controller
Philips Semiconductors
15.1.3 HcCommandStatus register (R/W: 02H/82H)
The HcCommandStatus register is a 4-byte register, and the bit allocation is given in
Table 39. This register is used by the HC to receive commands issued by the HCD,
and it also reflects the current status of the HC. To the HCD, it appears to be a ‘write
to set’ register. The HC must ensure that bits written as logic 1 become set in the
register while bits written as logic 0 remain unchanged in the register. The HCD may
issue multiple distinct commands to the HC without concern for corrupting previously
issued commands. The HCD has normal read access to all bits.
The SchedulingOverrunCount (SOC) field indicates the number of frames with which
the HC has detected the scheduling overrun error. This occurs when the Periodic list
does not complete before the End-of-Frame (EOF). When a scheduling overrun error
is detected, the HC increments the counter and sets the SchedulingOverrun (SO)
field of the HcInterruptStatus register.
Code (Hex): 02 — read
Code (Hex): 82 — write
Table 39: HcCommandStatus register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
Symbol
Reset
Access
Bit
reserved
SOC[1:0]
-
-
-
-
-
-
-
-
-
-
-
-
0
R
9
0
R
8
15
14
13
12
11
10
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
Symbol
Reset
Access
reserved
HCR
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
73 of 150
NXP [ NXP ]
